A resistor-based memory array 200, such as that depicted in FIG. 1, typically contains intersecting row lines 210 and column lines 220 which are interconnected by resistive memory cells 230 at the cross point of the row and column lines. A magnetic random access memory (MRAM) is one example of a memory device which includes resistive memory cells arranged as shown in FIG. 1.
FIG. 1 shows a portion of a resistive memory device. The device includes an array 200 of Magnetic Random Access Memory (MRAM) elements, a plurality of electrically conductive row lines 210, and a plurality of electrically conductive column lines 220. Each row line is connected to each of the plurality of column lines by a respective MRAM resistive element 230. If resistive memory array consists of 1024 rows and 1024 columns, i.e., approximately 1 million cells, and each cell has a resistance of 1.2 MΩ or 800 KΩ, depending on its logic state, the collective resistance when all rows and all columns, except for those associated with the selected cell, are respectively shorted together will be approximately 1KΩ. Typically during the read process, a voltage is impressed across a selected row or cell, resulting in a voltage at node “A,” as a result of current flow through memory cell 130 connected to node “A.”
A plurality of switches 240, are respectively switchingly connected between one of the row lines and a first source of constant potential (ground) 250. The switches may be implemented as transistors, or may be a form of other programmable switches that are known in the art. A plurality of sensing circuits 260, are respectively connected to the plurality of column lines 220. Each sensing circuit 260 includes a source of constant electrical potential (VA) which is applied to the respective column line. A plurality of pull-up voltage sources 215, supplying voltage VA, are respectively connected to each of the plurality of row lines 210.
In operation, switch 240, such as switch 270 associated with a particular row line 280, is closed so as to bring that row line to the ground potential and a particular column line, e.g., 320 is sensed to read the resistance value of a particular resistor 310.
FIG. 2, shows the resulting electrical circuit for the relevant portion 300 of the memory array when row 280 is grounded. As shown, memory element 310 to be sensed is connected between a grounded row line 280 and a particular column line 320. Also connected to the column line 320 are a plurality of other resistive memory elements (e.g. elements 330, 340, 350, 360, 370) each of which is connected at its opposite end to a pull-up voltage source VA 215 through a respective row line 210. In addition, a sensing circuit 400 is connected to the column line 320. The sensing circuit 400 includes a voltage supply (not shown) that maintains the column line 320 at the potential of the voltage source VA.
The other resistive memory elements (those tied to ungrounded row lines) 330, 340, 350, 360, 370, form an equivalent resistance referred to as sneak resistance. The effective resistance of the sneak resistance is small. A typical value for the sneak resistance might be 1 KΩ. Nevertheless, because both ends of each ungrounded element 320, 340, 350, 360, 370 are ideally maintained at the same potential as the column line 320 (e.g., VA), net current flow through the sneak resistance is desirably nearly zero.
In contrast, a measurable current flows through the grounded resistive memory element 310. This measurable current allows the sensing circuit 400 to evaluate the resistance of the memory element 310 by the sensing circuit 400. Since significant current can flow in a resistive memory array when sensing the value of the memory element, a continuous power draw on the memory array will require a relatively large current draw from a power source.